1. Field of the Invention
The present invention relates to a silicon carbide semiconductor device, more particularly, a silicon carbide semiconductor device having a gate electrode.
2. Description of the Background Art
Japanese Patent Laying-Open No. 7-326755 discloses a trench gate type power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this MOSFET, an n type epitaxial layer and a p type epitaxial layer are stacked in this order on an n+ type single-crystal SiC substrate. In a predetermined region of a surface of the p type epitaxial layer, an n+ source region is formed as a semiconductor region. Further, a trench is formed in a predetermined location of the surface of the p type epitaxial layer. This trench extends through the n+ source region and the p type epitaxial layer to reach the n type epitaxial layer, has side surfaces perpendicular to the surface of the p type epitaxial layer, and has a bottom surface parallel to the surface of the p type epitaxial layer. As a method for forming the n+ source region, an ion implantation method is disclosed which is performed onto the p type epitaxial layer using a mask material.
The above-described publication recites no detailed form of a boundary between the n type epitaxial layer and the p type epitaxial layer. Generally, when an n type epitaxial layer and a p type epitaxial layer are stacked in this order, a region having a donor type impurity and an acceptor type impurity mixed with each other and accordingly canceled by each other is formed in the vicinity of a boundary between the n type epitaxial layer and the p type epitaxial layer. The vicinity of the boundary is a region in which a depletion layer is to be formed due to pn junction. Hence, when a region having a low effective impurity concentration, i.e., a region in which a generation current is likely to be generated is formed to be thick in this region, a leakage current will be large due to the increase of the generation current.
Meanwhile, according to the above-described publication, the n+ source region is formed by implanting ions into the upper portion of the p type epitaxial layer. Hence, after the implantation, lattice defects resulting from the ion implantation are generated in a portion of the p type epitaxial layer that faces the n+ source region. In other words, lattice defects are increased in the depletion layer in the vicinity of the boundary between the p type epitaxial layer and the n+ source region. This results in increased generation current in the depletion layer, which leads to a large leakage current.
Further, when forming the n+ source region by means of the ion implantation, a certain amount of the donor type impurity for the formation thereof is also implanted into the portion of the p type epitaxial layer that faces the n+ source region. With the cancelation by this donor type impurity, the effective density of the acceptor type impurity is decreased in the portion of the p type epitaxial layer that faces the n+ source region. As a result, the region having a low effective impurity concentration, i.e., the region in which the generation current is likely to be generated is formed to be thick in the vicinity of the boundary between the p type epitaxial layer and the n+ source region. Accordingly, the leakage current becomes large due to the generation current.